It’s predominantly the first one.
They have made a few unique design decisions, but is a fairly conservative “boring” RISC design.
The only thing remarkable I can think of of the core ISA is the fact that they have no conditional status registers (no NZVC bits), so you have to kind of combine conditions and branches together, but that’s not exactly unprecedented (MIPS did something similar).
In the ISA extensions, there is still some instability and disagreement about the best ISA design for some parts.
Just the fact that RISC-V is going to have both SIMD and Vector instructions is a bit unique, but probably won’t make a huge difference.
But it’s a fairly boring RISC design which is free and open and without any licensing hoops to jump through, which is the most interesting bit.
It’s predominantly the first one. They have made a few unique design decisions, but is a fairly conservative “boring” RISC design. The only thing remarkable I can think of of the core ISA is the fact that they have no conditional status registers (no NZVC bits), so you have to kind of combine conditions and branches together, but that’s not exactly unprecedented (MIPS did something similar).
In the ISA extensions, there is still some instability and disagreement about the best ISA design for some parts. Just the fact that RISC-V is going to have both SIMD and Vector instructions is a bit unique, but probably won’t make a huge difference.
But it’s a fairly boring RISC design which is free and open and without any licensing hoops to jump through, which is the most interesting bit.